Exemplary embodiments of the present invention relate to a semiconductor device design technique and more particularly, to a sampling circuit of a semiconductor device.
The sampling operation for a digital signal is performed by detecting a logic level of the digital signal in synchronism with a reference clock. In detail, while performing the sampling operation, it is determined whether the logic level of the digital signal has a logic high level or a logic low level at a certain edge of the reference clock. In order to secure a reliable sampling operation, the digital signal is held valid and constant for specified periods before and after the certain edge of the reference clock, which periods are called the setup time and the hold time, respectively.
FIG. 1 shows graphs illustrating a general sampling operation for a digital signal.
As shown, the digital signal of case (A) maintains a certain logic level for a longer period than that of case (B). The set up time and the hold time are set before and after the certain edge of the reference clock for specified periods, respectively, in both cases (A) and (B). Although FIG. 1 only shows that the sampling operation is performed at a rising edge of the reference clock, it is also possible to perform the sampling operation at a falling edge of the reference clock.
Since the digital signal of case (A) maintains the certain logic level for a relatively longer period, there are sufficient margins before the set up time and after the hold time. Accordingly, the sampling operation to the digital signal of case (A) can be more reliably performed even when the edge of the reference clock moves depending on the process, voltage, and temperature (PVT) conditions.
In case (B), the digital signal holds the certain logic level only for the set up time and the hold time (i.e., without margins). Therefore, it is difficult to perform the sampling operation correctly when the edge of the reference clock moves according to the PVT conditions.
The period where the digital signal maintains the certain level is determined by a frequency of the digital signal. That is, the frequency of the digital signal of case (A) is lower than that of case (B). Currently, the operation speed of the semiconductor device continuously increases and, therefore, the frequency of the digital signal inputted to the semiconductor device is required to be continuously decreased. Accordingly, since the period where the digital signal maintains the valid and constant level continuously decreases, it becomes more difficult to secure the reliable sampling operation for the digital signal and the correct operation of the semiconductor device.